Job Description:
seeking for Subject Matter Expert in FPGA design. Candidate must have in-dept low level FPGA technology understanding on parallel gate level computing. This role will require C/C skillset instead of traditional RTL but require strong FPGA skillset and level of thinking for the design and verification element in timing and complex parallel computing and reconfiguration for algorithm development. Strong understanding of parallel computing at gate level with timing closure is necessary for this role.
Develops, designs, verifies, and documents Field Programmable Gate Arrays (FPGA) development.
Determines architecture design, logic design, and system simulation.
Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization.
Typically uses specialized equipment to establish operation data, conduct experimental tests, and evaluate results.
Support Circuit card designer with trade studies.
Develop and release design requirement specifications for product.
Support of production environment in debugging and troubleshooting FPGA related issues in a production environment will be a critical component of this particular role.
Required Experience:
12 years of experience in FPGA design and verification is a requirement.
7 Years experience with C/C Programming language.
4 years experience with Client processors for embedded real-time system
12 Years experience integrating FPGA solution on hardware and design validation including simulation validation.
Level 5: BS 11 YRS or MS 9 YRS
Nesco Resource provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.
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seeking for Subject Matter Expert in FPGA design. Candidate must have in-dept low level FPGA technology understanding on parallel gate level computing. This role will require C/C skillset instead of traditional RTL but require strong FPGA skillset and level of thinking for the design and verification element in timing and complex parallel computing and reconfiguration for algorithm development. Strong understanding of parallel computing at gate level with timing closure is necessary for this role.
Develops, designs, verifies, and documents Field Programmable Gate Arrays (FPGA) development.
Determines architecture design, logic design, and system simulation.
Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization.
Typically uses specialized equipment to establish operation data, conduct experimental tests, and evaluate results.
Support Circuit card designer with trade studies.
Develop and release design requirement specifications for product.
Support of production environment in debugging and troubleshooting FPGA related issues in a production environment will be a critical component of this particular role.
Required Experience:
12 years of experience in FPGA design and verification is a requirement.
7 Years experience with C/C Programming language.
4 years experience with Client processors for embedded real-time system
12 Years experience integrating FPGA solution on hardware and design validation including simulation validation.
Level 5: BS 11 YRS or MS 9 YRS
Nesco Resource provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.